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rev.2.00 S1R72U16 data sheet
notice no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko epson. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit a nd, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export license from the ministry of economy, trade and industry or other approval from another government agency. all other product names mentioned herein are trademarks and/or registered trademarks of their respective companies. ?seiko epson corporation 2008, all rights reserved.
scope this document applies to the S1R72U16 ide device - usb 2.0 host bridge lsi. notice before using the S1R72U16, carefully read the sections ?special use case for S1R72U16? and ?S1R72U16 errata.?
S1R72U16 data sheet (rev. 2.00) epson i table of contents 1. over view............................................................................................................................................ 1 2. feat ures .................................................................................................................... ......................... 2 3. block diagram ............................................................................................................... .................... 4 4. functi on s........................................................................................................................................... 5 4.1 main cp u i/ f ................................................................................................................... ........... 5 4.1.1 ide dev ice contro ller ........................................................................................................ 5 4.1.2 cpuif.......................................................................................................................... ...... 5 4.2 usb host ....................................................................................................................... ............. 5 4.3 gpi ............................................................................................................................................. 5 4.4 gpo ........................................................................................................................................... 5 4.5 sio ............................................................................................................................................. 6 4.6 osc ............................................................................................................................................ 6 5. pin layout diagram .......................................................................................................... ................ 7 6. pin functions ............................................................................................................... ..................... 8 6.1 ide mode....................................................................................................................... ............. 8 6.2 cpu m ode ....................................................................................................................... ......... 11 7. regi ster .................................................................................................................... ....................... 12 7.1 register map ............................................................................................................................ 12 7.1.1 ide mode regi ster map .................................................................................................. 12 7.1.2 cpu mode regi ster map ................................................................................................. 12 7.2 registers ...................................................................................................................... ............ 13 7.2.1 dat a r egister .................................................................................................................. 13 7.2.2 error re gist er ................................................................................................................. . 13 7.2.3 feature re gister .............................................................................................................. 13 7.2.4 sector count register ..................................................................................................... 13
ii epson S1R72U16 data sheet (rev. 2.00) 7.2.5 lba low re gister............................................................................................................ 13 7.2.6 lba mid r egister............................................................................................................. 14 7.2.7 lba high re gister ........................................................................................................... 14 7.2.8 dev ice re gister ............................................................................................................... 14 7.2.9 s tatus r egist er ................................................................................................................ 14 7.2.10 command r egister ......................................................................................................... 14 7.2.11 alternate s tat us register................................................................................................. 15 7.2.12 dev ice contro l register................................................................................................... 15 8. electrical ch aracteristics .................................................................................................. ............. 16 8.1 absolute max i mum ra tings ...................................................................................................... 16 8.2 recommended operat ing conditions ....................................................................................... 16 8.3 dc characte ristic s............................................................................................................. ....... 17 8.3.1 current cons umption ...................................................................................................... 17 8.3.2 input charac teristics ........................................................................................................ 18 8.3.3 output charac teristi cs ..................................................................................................... 19 8.3.4 pin cap aci tance .............................................................................................................. 20 8.4 ac characte ristic s............................................................................................................. ....... 21 8.4.1 reset t i ming ................................................................................................................... 21 8.4.2 clock t iming................................................................................................................... . 21 8.4.3 usb i/f timing ................................................................................................................ 22 8.4.4 ide dev ice i/f timing...................................................................................................... 22 8.4.5 cpuif t imi ng (pio ) ........................................................................................................ 23 8.4.6 cpuif t imi ng (dma )....................................................................................................... 24 8.4.7 serial i/f t iming .............................................................................................................. 25 9. connecti on example s ......................................................................................................... ........... 26 10. external dime nsion s diagram ................................................................................................ ..... 27 10.1 pfbga8 ux81 ..................................................................................................................... ..... 27
S1R72U16 data sheet (rev. 2.00) epson iii 10.2 qfp14- 80 ....................................................................................................................... .......... 28 11. product codes .............................................................................................................. ................ 29
1. overview S1R72U16 data sheet (rev. 2.00) epson 1 1. overview the S1R72U16 is an ide device - usb 2.0 host bridge lsi that supports usb2.0-compliant high-speed mode. the main cpu is capable of controlling usb storage devices connected to this lsi as ide devices. no usb driver is required. usb devices that can be connected to this lsi are bulk-only transport mass storage class devices (e.g., usb memory) and hub devices.
2. features 2 epson S1R72U16 data sheet (rev. 2.00) 2. features ? easy use/connect (ide bus connection) allows usb devices to be controlled as ide devices the main cpu is capable of controlling usb storag e devices connected to this lsi as ide devices. this lsi handles connection processing for the usb hub, no usb driver is required at the main cpu. an ata/atapi driver should be installed at the main cpu. a main cpu with an installed ata/atapi driver is capable of controlling usb storage devices via this lsi. ? easy use/connect (cpu bus connection) also permits cpu bus connections (i nterface voltage: 1.8 v to 3.3 v) the lsi can also be connected to a memory bus to connect to the main cpu without an ide bus. an ata/atapi driver should be installed in the main cpu. the registers used to control this lsi are ata task file registers. ? high-speed transfer transfer rate 31 mb/s (seiko epson figures) transfer rates of up to 31 mb/s can be achieved with ata100 and usb high-speed connection. ? embedded host silicon authentication high-quality usb signal this lsi includes an embedded host function (i ncluding authentication software) for silicon authentication. the S1R72U16 usb 2.0 pcb design guide and S1R72U16 embedded host compliance manual are also provided to help the user obtain usb logo certification. ? product (system) develo pment support functions history display lsi internal processing history can be displayed using the serial (asynchronous) interface. the S1R72U16 development support manual provides detailed information on this function. this function and the manual provide support for product (system) development. ? manuals and tools development manuals and tools (bridge board) the following manuals are provided in addition to this data sheet: ? S1R72U16 technical manual ? S1R72U16 application note ? S1R72U16 development support manual ? S1R72U16 usb 2.0 pcb design guide ? S1R72U16 embedded host compliance manual
2. features S1R72U16 data sheet (rev. 2.00) epson 3 ? S1R72U16 evaluation board manual an ide device - usb 2.0 host bridge board is also provided for system evaluations in the early stages of product (system) development. * * please contact your nearest seiko epson sales office to obtain the ide device - usb 2.0 host bridge board.
3. block diagram 4 epson S1R72U16 data sheet (rev. 2.00) 3. block diagram fifo ide device controller xreset transceiver macro usb host sie dp dm r1 vbusen osc test circuit* tsten, atpgen, burnin vbusflg bridge sequencer cpuif main cpu i/f selector ataxatapi sio debug i/f* dbgdclk, dbgdt, dbgst sclk0 sin0 sout0 2x1 cpuxiide xo xi clksel gpo gpi xchgint hda_t[2:0] / ca[2:0] xhior_t / xrd xhiow_t / xwr xhreset_t / xhreset csel_t / csel xhdmack_t / xdack hdmarq_t / xdreq hiordy_t / - hdd_t[15:0] / cd[15:0] xhcs_t[1:0] / xcs, ca[3] hintrq_t / xint xhdasp_t /- xhpdiag_t / - xcd0 xcd1 pll_locked complianceerror[3:0] figure 3.1 block diagram * fix the debug i/f and test circuit pins strictly as described in ?6. pin functions?. they are not intended for use by users.
4. functions S1R72U16 data sheet (rev. 2.00) epson 5 4. functions 4.1 main cpu i/f this lsi can be used as either of the following connections to the main cpu. ? ide bus connection (interface voltage: 3.3 v) ? cpu bus connection (interface voltage: 1.8 v to 3.3 v) bus connection is selected by using the mode setting pin cpuxide (port02). 4.1.1 ide device controller this block operates when ide bus connection is selected. it supports ata/atapi-6. ? pio transfer modes 0 to 4 ? multi word dma transfer modes 0 to 2 ? ultra dma transfer modes 0 to 5 4.1.2 cpuif this block operates when cpu bus connection is selected. the registers used to control this lsi are ata task file registers. it supports pio and dma (*) transfer. * for dma transfer, the main cpu must provide a dma master function that complies with the dma specifications of this lsi. 4.2 usb host the usb host function complies with the usb 2.0 (universal serial bus specification revision 2.0) standards. it supports hs (480 mbps) and fs (12 mbps) speed modes. usb host function is controlled by the bridge sequencer block inside th e lsi. usb devices that can be connected to this lsi are bulk-only transport mass storage class devices (e.g., usb memory) and hub devices. 4.3 gpi these are the mode setting pins for selecting the command system, number of connected devices, and interface to the main cpu. for detailed information, see the S1R72U16 technical manual . 4.4 gpo these pins are used to issue notification of usb storage device connections, internal pll operation status, and nsf (no silent failure). for detailed information, see the S1R72U16 technical manual .
4. functions 6 epson S1R72U16 data sheet (rev. 2.00) 4.5 sio this block is used to display the product (system) development support function history. for detailed information, see the S1R72U16 development support manual . 4.6 osc this oscillator circuit supports a 12 mhz/24 mhz cr ystal oscillator. the 12 mhz or 24 mhz clock is selected using the clksel pin.
5. pin layout diagram S1R72U16 data sheet (rev. 2.00) epson 7 5. pin layout diagram 123456789 a tsten atpgen xo xi hdd3_t iovdd hdd8_t hdd10_t nc a b lvdd vss lvdd hdd0_t hdd4_t hdd6_t hdd9_t hdd11_t lvdd b c r1 vss clksel hdd1_t hdd5_t hdd7_t hdd12_t hdd13_t hdd14_t c d hvdd burnin vss hdd2_t hda0_t hda1_t hdd15_t hda2_t vss d e dm vss vss port00 port01 xhcs1_t xhcs0_t xhdasp_t xhreset_t e f dp hvdd vbusflg port02 hintrq_t port11 xhpdiag_t port17 csel_t f g lvdd vss vbusen xreset xhiow_t port10 port13 port15 port16 g h dbgdclk dbgdt dbgst sin0 hdmarq_t hiordy_t port12 port14 iovdd h j nc hvdd sout0 sclk0 xhdmack_t xhior_t vss lvdd nc j 123456789 S1R72U16/pfbga8ux81 top view figure 5.1 pfbga8ux81 package pin layout diagram (*) lvdd hdd11_t hdd12_t hdd13_t hdd14_t hdd15_t hda2_t vss hda1_t hda0_t xhcs1_t xhcs0_t xhreset_ t xhdasp_t xhpdiag_t csel_t port17 port16 port15 iovdd 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 hdd10_t 61 40 lvdd hdd9_t 62 39 port14 hdd8_t 63 38 port13 hdd7_t 64 37 port12 hdd6_t 65 36 port11 iovdd 66 35 port10 hdd5_t 67 34 vss hdd4_t 68 33 xhior_t hdd3_t 69 32 hiordy_t hdd2_t 70 31 xhiow_t hdd1_t 71 30 hdmarq_t hdd0_t 72 29 xhdmack_t vss 73 28 hintrq_t xi 74 27 port01 xo 75 26 port00 lvdd 76 25 port02 clksel 77 24 xreset burnin 78 23 sclk0 atpgen 79 22 sout0 tsten 80 21 hvdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 lvdd vss r1 vss hvdd dm vss dp hvdd lvdd vss nc nc vss vbusflg vbusen dbgdclk dbgdt dbgst sin0 S1R72U16/qfp14-80 figure 5.2 qfp14-80 package pin layout diagram (*) * shown here with pin names for ide mode connection.
6. pin functions 8 epson S1R72U16 data sheet (rev. 2.00) 6. pin functions 6.1 ide mode general (iovdd system) bga qfp name i/o reset details g4 24 xreset in - reset signal c3 77 clksel in xi clock input selection 1: 24mhz 0: 12mhz osc (lvdd system) bga qfp name i/o reset details a4 74 xi in - internal oscillator circuit input 12mhz/24mhz a3 75 xo out - internal oscillator circuit output test (lvdd system) bga qfp name i/o reset details a1 80 tsten in(pd) - test pin (*) a2 79 atpgen in(pd) - test pin (*) d2 78 burnin in(pd) - test pin (*) pd: using pull-down i/o * the lsi features internal pull-down, but low fixing is recommended on the circuit board. usb bga qfp name i/o reset details c1 3 r1 in - reference voltage setting pin connect 6.2 k ? 1% resistor between vss. f1 8 dp bi hi-z usb data line data+ e1 6 dm bi hi-z usb data line data- f3 15 vbusflg in(pu) - usb power switch fault detection signal 1: normal, 0: error cmos schmitt input g3 16 vbusen out low usb power switch control signal pu: using pull-up i/o
6. pin functions S1R72U16 data sheet (rev. 2.00) epson 9 ide device i/f (iovdd system) bga qfp name i/o reset details d8 54 hda2_t in - d6 52 hda1_t in - d5 51 hda0_t in - ide register address e6 50 xhcs1_t in - control register access chip selection e7 49 xhcs0_t in - command block register access chip selection j6 33 xhior_t in - ide read strobe g5 31 xhiow_t in - ide write strobe h5 30 hdmarq_t out low dma transfer request j5 29 xhdmack_t in - dma transfer acknowledge h6 32 hiordy_t out (pu) hi-z ide register ready signal (*) f5 28 hintrq_t out low ide interrupt request e9 48 xhreset_t in - ide bus reset e8 47 xhdasp_t bi(pu) hi-z drive enable/slave drive present (*) f7 46 xhpdiag_t bi(pu) hi-z diagnosis sequence end signal ( * ) f9 45 csel_t in - drive selection d7 55 hdd15_t bi hi-z c9 56 hdd14_t bi hi-z c8 57 hdd13_t bi hi-z c7 58 hdd12_t bi hi-z b8 59 hdd11_t bi hi-z a8 61 hdd10_t bi hi-z b7 62 hdd9_t bi hi-z a7 63 hdd8_t bi hi-z c6 64 hdd7_t bi hi-z b6 65 hdd6_t bi hi-z c5 67 hdd5_t bi hi-z b5 68 hdd4_t bi hi-z a5 69 hdd3_t bi hi-z d4 70 hdd2_t bi hi-z c4 71 hdd1_t bi hi-z b4 72 hdd0_t bi hi-z ide data bus pu: using pull-up i/o * lsi internal pull-up is disabled in ide mode. serial i/f (hvdd system) bga qfp name i/o reset details j4 23 sclk0 i(pu) not used (*) h4 20 sin0 i(pu) - asynchronous serial data in j3 22 sout0 o high asynchronous serial data out pu: using pull-up i/o * set to open or pull-up.
6. pin functions 10 epson S1R72U16 data sheet (rev. 2.00) debug i/f (hvdd system) bga qfp name i/o reset details h1 17 dbgdclk o high not used (*1) h2 18 dbgdt bi(pu) - not used (*2) h3 19 dbgst o low not used (*1) pu: using pull-up i/o *1: set to open or pull-up. *2: the lsi features internal pull-up, but an external pull-up of approximately 10 k ? is recommended. gpio (iovdd system) bga qfp name i/o reset details e4 26 port00 (ataxatapi) i - setting pin 1: ata mode, 0: atapi mode e5 27 port01 (2x1) i - setting pin 1: two-device mode, 0: one-device mode f4 25 port02 (cpuxide) i - setting pin 1: cpu mode, 0: ide mode g6 35 port10 (xchgint) o - storage device connection detection interrupt 1: -, 0: connection detection f6 36 port11 (xcd0) o - storage device 0 detection 1: -, 0: detect h7 37 port12 (xcd1) o - storage device 1 detection 1: -, 0: detect g7 38 port13 (pll_locked) o - pll oscillation start 1: oscillation start, 0: no oscillation h8 39 port14 (complianceerr0) o - unsupported device 1: error, 0: - g8 42 port15 (complianceerr1) o - too many devices 1: error, 0: - g9 43 port16 (complianceerr2) o - too many hubs 1: error, 0: - f8 44 port17 (complianceerr3) o - vbus over current 1: error, 0: - power bga qfp name voltage details d1, f2, j2 5, 9, 21 hvdd 3.3v usb, uart, debug i/f power supply a6, h9 41, 66 iovdd 3.3v to 1.8v ide i/f and gpio power supply b1, g1, b3, j8, b9 1, 10, 40, 60, 76 lvdd 1.8v internal power supply, test power supply, osc power supply b2, c2, e2, g2, d3, e3, j7, d9 2, 4, 7, 11, 14, 34, 53, 73 vss 0v gnd
6. pin functions S1R72U16 data sheet (rev. 2.00) epson 11 6.2 cpu mode cpu memory bus i/f (iovdd system) bga qfp name i/o reset details d8 54 ca2 in - d6 52 ca1 in - d5 51 ca0 in - address e6 50 xcs in - chip selection e7 49 ca3 in - address j6 33 xrd in - read strobe g5 31 xwr in - write strobe h5 30 xdreq out high dma transfer request j5 29 xdack in - dma transfer acknowledge h6 32 - out(pu) hi-z not used (*) f5 28 xint out high interrupt request e9 48 xhreset in - bus reset e8 47 - bi(pu) hi-z not used (*) f7 46 - bi(pu) hi-z not used (*) f9 45 csel in - drive selection d7 55 cd15 bi hi-z c9 56 cd14 bi hi-z c8 57 cd13 bi hi-z c7 58 cd12 bi hi-z b8 59 cd11 bi hi-z a8 61 cd10 bi hi-z b7 62 cd9 bi hi-z a7 63 cd8 bi hi-z c6 64 cd7 bi hi-z b6 65 cd6 bi hi-z c5 67 cd5 bi hi-z b5 68 cd4 bi hi-z a5 69 cd3 bi hi-z d4 70 cd2 bi hi-z c4 71 cd1 bi hi-z b4 72 cd0 bi hi-z data bus pu: using pull-up i/o * set to open or pull-up. lsi internal pull-up resistor is enabled in cpu mode. for detailed information on pins other than those described above, see ?6.1 ide mode?.
7. register 12 epson S1R72U16 data sheet (rev. 2.00) 7. register 7.1 register map 7.1.1 ide mode register map xhcs1_t xhcs0_t hda2_t hda1_t hda0_t read write pin register l h l l l none l h l l h none l h l h l none l h l h h none l h h l l none l h h l h none l h h h l alternate status l h h h h none l h l l l data (16bit) l h l l h error l h l h l sector count l h l h h lba low l h h l l lba mid l h h l h lba high l h h h l device l h h h h command device control status feature figure 7.1 ide mode register map 7.1.2 cpu mode register map xcs ca3 ca2 ca1 ca0 read write pin register l h l l l none l h l l h none l h l h l none l h l h h none l h h l l none l h h l h none l h h h l alternate status l h h h h none l l l l data (16bit) l l l h error l l h l sector count l l h h lba low l h l l lba mid l h l h lba high l h h l device l h h h command device control status feature l l l l l l l l figure 7.2 cpu mode register map
7. register S1R72U16 data sheet (rev. 2.00) epson 13 7.2 registers these are ata task file register s. for detailed information, see at attachment with packet interface ? 6 (ata/atapi-6) . 7.2.1 data register this re gister permits reads/writes. it is used for data transfers. it supports 16-bit access only. bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 data[15:8] bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 data[7:0] 7.2.2 error register this is a read-only register. the register valu e is enabled when the status register err bit is ?1?. bit assignments and values vary, depending on the ata/atapi command. # # # # # abrt # # bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 7.2.3 feature register this is a write-only register. writing to this register depends on the ata/atapi command. bit assignments and values are defined for each command. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 features byte 7.2.4 sector count register this register permits reads/writes and sets the number of sectors for data transfers. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sector count byte 7.2.5 lba low register this register permits reads/writes and sets lba [7:0]. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 lba low byte
7. register 14 epson S1R72U16 data sheet (rev. 2.00) 7.2.6 lba mid register this register permits reads/writes and sets lba [15:8]. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 lba mid byte 7.2.7 lba high register this register permits reads/writes and sets lba [23:16]. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 lba high byte 7.2.8 device register this register permits reads/writes. bit assignments and values vary, depending on the ata/atapi command. obsolute # obsolute dev # # # # bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 7.2.9 status register this read-only register is updated to indicate status when a command is executed. reading this register when the hintrq_t signal is asserted cause to nagate the hintrq_t signal. bsy drdy df # drq obsolute chgint err bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit 1 chgint this bit, unique to this lsi, indicates whether a usb storage device is connected (using the bit dropped as of at attachment with packet interface ? 6 (ata/atapi-6) ). the xchgint signal status can be read off inverted. for detailed information, see the S1R72U16 technical manual . 7.2.10 command register this is a write-only register. the register command is executed immediately on being written. issuing the command (writing to this register) when the hintrq_t signal is asserted cause to nagate the hintrq_t signal. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 command code
7. register S1R72U16 data sheet (rev. 2.00) epson 15 7.2.11 alternate status register this read-only register is the same as the status register except when the hintrq_t signal is not altered. 7.2.12 device control register this w rite-only register is used to reset the hintrq_t signal control and software and to support big drive. hob # # # # srst nien # bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
8. electrical characteristics 16 epson S1R72U16 data sheet (rev. 2.00) 8. electrical characteristics 8.1 absolute maximum ratings (v ss =0v) item code rating units hvdd vss-0.3 to 4.0 v iovdd vss-0.3 to 4.0 v power supply voltage lvdd vss-0.3 to 2.5 v hvi vss-0.3 to hvdd+0.5 v iovi vss-0.3 to iovdd+0.5 v input voltage (*) lvi vss-0.3 to lvdd+0.5 v hvo vss-0.3 to hvdd+0.5 v output voltage (*) iovo vss-0.3 to iovdd+0.5 v output current/pin iout 10 ma storage temperature tstg -65 to 150 c * check the power supply system information in ?6. pin functions? for the corresponding pins. 8.2 recommended operating conditions item code min typ max units hvdd 3.00 3.30 3.60 v iovdd (*1) 1.65 1.80 to 3.30 3.60 v power supply voltage lvdd 1.65 1.80 1.95 v hvi -0.3 - hvdd+0.3 v iovi -0.3 - iovdd+0.3 v input voltage (*2) lvi -0.3 - lvdd+0.3 v ambient temperature t a -40 25 85 c *1: use with 3.3 v (typ) in ide mode. *2: check the power supply system information in ?6. pin functions? for the corresponding pins. [precautions for power-on sequence] power to the hvdd and iovdd s hould be turned on/off with lvdd confirmed. (*) ? power-on: lvdd (hvdd, iovdd) ? power-off: (hvdd, iovdd) lvdd * reliability issues may arise if lvdd is cut o ff and hvdd or iovdd or both are on continuously for 1 second or longer.
8. electrical characteristics S1R72U16 data sheet (rev. 2.00) epson 17 8.3 dc characteristics 8.3.1 current consumption item code conditions min typ max units power supply current (*) iddh hvdd = 3.6v - 17.0 ma iddch iovdd = 3.6v - 2.0 ma iddcl iovdd = 1.95v - 1.5 ma power current iddl lvdd = 1.95v - 65.0 ma static current vin = hvdd,iovdd,lvdd or vss hvdd = 3.6v iovdd = 3.6v power current idds lvdd = 1.95v - - 70 a input leak input leak current il hvdd = 3.6v iovdd = 3.6v lvdd = 1.95v hvih = hvdd iovih = iovdd lvih = lvdd -5 - 5 a * mean operating current at recommen ded operating conditions (ta = 25c)
8. electrical characteristics 18 epson S1R72U16 data sheet (rev. 2.00) 8.3.2 input characteristics item code conditions min typ max units input characteristics pin: tsten, atpgen, burnin, xi ?h? level input voltage vih1 lvdd = 1.95v 1.27 - - v ?l? level input voltage vil1 lvdd = 1.65v - - 0.57 v input characteristics pin: hdd_t[15:0], ha d_t[2:0], xhcs_t[1:0 ], xhior_t, xhiow_t, xhdmack_t, xhreset_t, xhdasp_t, xhpdiag_t, csel_t ?h? level input voltage vih2 iovdd = 3.6v iovdd = 1.95v 2.0 1.27 - - v ?l? level input voltage vil2 iovdd = 3.0v iovdd = 1.65v - - 0.8 0.57 v input characteristics pin: xres et, clksel, port00, port01, port02 ?h? level input voltage vih3 iovdd = 3.6v iovdd = 1.95v 2.2 1.20 - - v ?l? level input voltage vil3 iovdd = 3.0v iovdd = 1.65v - - 0.8 0.50 v input characteristics (schmitt) pin: sclk0, sin0, dbgdt, vbusflg ?h? level trigger voltage vt1+ hvdd = 3.6v 1.4 - 2.7 v ?l? level trigger voltage vt1- hvdd = 3.0v 0.6 - 1.8 v hysteresis voltage v1 hvdd = 3.0v 0.3 - - v schmitt input characteristics (usb: fs) pin: dp, dm ?h? level trigger voltage vtu+ hvdd = 3.6v 1.1 - 1.8 v ?l? level trigger voltage vtu- hvdd = 3.0v 1.0 - 1.5 v hysteresis voltage vu hvdd = 3.0v 0.1 - - v input characteristics (usb:fs differential input) pin: dp, dm pair differential input sensitivity vdsu hvdd = 3.0v differential input voltage 0.8v to 2.5v - - 0.2 v input characteristics pin: sclk0, sin0, dbgdt pull-up resistance rplu1h vi = hvdd 25 50 120 k input characteristics pin: hintrq _t, xhdasp_t, xhpdiag_t, vbusflg pull-up resistance rplu2h vi = hvdd or iovdd 50 100 240 k input characteristics pin: atpgen, burnin pull-down resistance rpld1l vi = lvdd 24 60 150 k input characteristics pin: tsten pull-down resistance rpld2l vi = lvdd 48 120 300 k input characteristics pin: vbus pull-down resistance rpldb vi = 5.0v 110 125 150 k
8. electrical characteristics S1R72U16 data sheet (rev. 2.00) epson 19 8.3.3 output characteristics (v ss =0v) item code conditions min typ max units output characteristics pin: hdd_t[15:0], hdmarq_t, hiordy_t, hintrq_t, xhdasp_t, xhpdiag_t ?h? level output voltage voh1 iovdd = 3.0v ioh = -4.0ma iovdd = 1.65v ioh = -2.0ma iovdd - 0.4 - - v ?l? level output voltage vol1 iovdd = 3.0v iol = 4.0ma iovdd = 1.65v iol = 2.0ma - - 0.4 v output characteristics pin: port10, port11, port12, port 13, port14, port15, port16, port17 ?h? level output voltage voh2 iovdd = 3.0v ioh = -2.0ma iovdd = 1.65v ioh = -1.0ma iovdd - 0.4 - - v ?l? level output voltage vol2 iovdd = 3.0v iol = 2.0ma iovdd = 1.65v iol = 1.0ma - - 0.4 v output characteristics pin: so ut0, dbgdclk, dbgdt, dbgst ?h? level output voltage voh3 hvdd = 3.0v ioh = -4.0ma hvdd - 0.4 - - v ?l? level output voltage vol3 hvdd = 3.0v iol = 4.0ma - - 0.4 v output characteristics pin: vbusen ?h? level output voltage voh4 hvdd = 3.0v ioh = -2.0ma hvdd - 0.4 - - v ?l? level output voltage vol4 hvdd = 3.0v iol = 2.0ma - - 0.4 v output characteristics (usb:fs) pin: dp, dm ?h? level output voltage vohuf hvdd = 3.0v 2.8 - - v ?l? level output voltage voluf hvdd = 3.6v - - 0.3 v output characteristics (usb:hs) pin: dp, dm ?h? level output voltage vohuh hvdd = 3.0v 360 - - mv ?l? level output voltage voluh hvdd = 3.6v - - 10.0 mv output characteristics pin: hdd_t[15:0], hdmarq_t, hiordy_t, hintrq_t, xhdasp_t, xhpdiag_t, sclk0, sin0, dbgdt off-state leakage ioz hvdd, iovdd = 3.6v voh = hvdd or iovdd vol = vss -5 - 5 a
8. electrical characteristics 20 epson S1R72U16 data sheet (rev. 2.00) 8.3.4 pin capacitance item code conditions min typ max units pin capacitance pin: all input pins input pin capacitance ci f = 1mhz hvdd = iovdd = lvdd = vss - - 8 pf pin capacitance pin: all output pins output pin capacitance co f = 1mhz hvdd = iovdd = lvdd = vss - - 8 pf pin capacitance pin: input/out put pins except dp and dm input/output pin capacitance cb f = 1mhz hvdd = iovdd = lvdd = vss - - 8 pf pin capacitance pin: dp and dm input/output pin capacitance (usb) cbu f = 1mhz hvdd = iovdd = lvdd = vss - - 11 pf
8. electrical characteristics S1R72U16 data sheet (rev. 2.00) epson 21 8.4 ac characteristics 8.4.1 reset timing xreset treset code details min typ max units treset reset pulse width 40 - - ns 8.4.2 clock timing code details min typ max units tcyc clock cycle (clksel = "l") 11.9988 12.000 12.0012 mhz xi tcycl tcych tcyc tcyc clock cycle (clksel = "h") 23.9976 24.000 24.0024 mhz tcycl tcych clock duty 45 50 55 %
8. electrical characteristics 22 epson S1R72U16 data sheet (rev. 2.00) 8.4.3 usb i/f timing complies with usb 2.0 universal serial bus specification revision 2.0 tandards. 8.4.4 ide device i/f timing complies with at attachment with packet interface ? 6 (ata/atapi-6) standards.
8. electrical characteristics S1R72U16 data sheet (rev. 2.00) epson 23 8.4.5 cpuif timing (pio) xcs, ca[3:0] tasu code details min typ max units tcy cycle 120/130 - - ns xrd, xwr cd[15:0](write) xdreq xdack cd[15:0](read) tspw twds twd h trds trdh trbf tahd tcy tasu address setup 25/30 - - ns tspw xrd/xwr pulse width 70/75 - - ns trds read data setup 20/15 - - ns trdh read data hold 5/5 - - ns trbf bus release 30/30 - - ns twds write data setup 20/25 - - ns twdh write data set hold 10/10 - - ns tahd address hold 10/10 - - ns pio read/write "high" "high" tsrc tsrc xrd/xwr recovery 25/30 - - ns * when using iovdd = 3.0 v to 3.6 v / when using iovdd = 1.8 v to 3.0 v (wide range) code details min typ max units trdh read data hold time 5/5 * 1 - - ns tahd address hold time 0/0 - - ns * when using iovdd = 3.0 v to 3.6 v / when using iovdd = 1.8 v to 3.0 v (wide range) * 1: the read data hold time will be 0 ns for address changes if the address hold time is less than 5 ns. S1R72U16 *** e200 ac characteristics note: the definition of ac shown above uses the description format specified in ata standards. consider the valid data output start time in a read operation as follows: 70 (xrd pulse width: min) -20 (read data setup: min) = 50 ns (when iovdd = 3.0 to 3.6 v)
8. electrical characteristics 24 epson S1R72U16 data sheet (rev. 2.00) 8.4.6 cpuif timing (dma) xcs, ca[3:0] tasu code details min typ max units tcy cycle 120/130 - - ns xrd, xwr cd[15:0](write) xdreq xdack cd[15:0](read) tspw twds twd h trds trdh trbf tahd tcy tasu address setup 25/25 - - ns tspw xrd/xwr pulse width 70/75 - - ns trds read data setup 20/15 - - ns trdh read data hold 5/5 - - ns trbf bus release 30/30 - - ns twds write data setup 20/25 - - ns twdh write data set hold 10/10 - - ns tahd address hold 10/10 - - ns dma read/write tnpw trdl tach tacs tspw xrd/xwr negate pulse width 25/30 - - ns trdl xdreq delay 35/45 - - ns tacs xdack setup 0/0 - - ns tach xdack hold 5/5 - - ns * when using iovdd = 3.0 v to 3.6 v / when using iovdd = 1.8 v to 3.0 v (wide range) code details min typ max units trdh read data hold time 5/5 * 1 - - ns tahd address hold time 0/0 - - ns * when using iovdd = 3.0 v to 3.6 v / when using iovdd = 1.8 v to 3.0 v (wide range) * 1: the read data hold time will be 0 ns for address chan g es if the address hold time is less than 5 ns. S1R72U16 *** e200 ac characteristics note: the definition of ac shown above uses the description format specified in ata standards. consider the valid data output start time in a read operation as follows: 70 (xrd pulse width: min) -20 (read data setup: min) = 50 ns (when iovdd = 3.0 to 3.6 v)
8. electrical characteristics S1R72U16 data sheet (rev. 2.00) epson 25 8.4.7 serial i/f timing code detail min typ max unit tbr baud rate - 19200 - bps sin0/sout0 tbr tbr
9. connection examples 26 epson S1R72U16 data sheet (rev. 2.00) 9. connection examples refer to the S1R72U16 evaluation board manual for usb i/f, ide i/f, cpu i/ f (in cpu mode), and serial i/f connection examples.
10. external dimensions diagram S1R72U16 data sheet (rev. 2.00) epson 27 10. external dimensions diagram 10.1 pfbga8ux81
10. external dimensions diagram 28 epson S1R72U16 data sheet (rev. 2.00) 10.2 qfp14-80
11. product codes S1R72U16 data sheet (rev. 2.00) epson 29 11. product codes table 11.1 product codes product code details S1R72U16b08e100 S1R72U16b08e200 pfbga8ux81 package S1R72U16f14e100 S1R72U16f14e200 qfp14-80 package
revision history revision history rev. page type details 05/14/2007 0.79 all pages new newly established 07/01/2007 1.00 8.3.1 8.3.2 8.3.3 8.4.5 8.4.6 8.4.7 addition addition addition addition addition addition spec. added spec. added(iovdd=1.8v) spec. added(iovdd=1.8v) spec. added spec. added serial i/f timing added scope add added ?notice.? 2 correct changed ?ide driver? to ?ata/atapi driver.? 6.1 and 6.2 correct changed setting of unused terminal from ?open? to ?open or pull-up.? 8.4.2 correct spec. corrected as follows: ?11.999? to ?11.9988? ?12.001? to ?12.0012 ?23.998? to ?23.9976? ?24.002? to ?24.0024? 10/15/2007 1.10 8.4.5 and 8.4.6 add added note regarding valid data output start time. 8.4.5 8.4.6 addition added S1R72U16 *** e200 timing. 04/21/2008 2.00 11 addition added S1R72U16 *** e200 product code.
international sales operations america epson electronics america, inc. headquarters 2580 orchard parkway san jose , ca 95131,usa phone: +1-800-228-3964 fax: +1-408-922-0238 sales offices northeast 301 edgewater place, suite 210 wakefield, ma 01880, u.s.a. phone: +1-800-922-7667 fax: +1-781-246-5443 europe epson europe electronics gmbh headquarters riesstrasse 15 muenchen bayern, 80992 germany phone: +49-89-14005-0 fax: +49-89-14005-110 asia epson (china) co., ltd. 7f, jinbao bldg.,no.89 jinbao st.,dongcheng district, beijing 100005, china phone: +86-10-6410-6655 fax: +86-10-6410-7320 shanghai branch 7f, block b, hi-tech bl dg., 900, yishan road, shanghai 200233, china phone: +86-21-5423-5522 fax: +86-21-5423-5512 epson hong kong ltd. 20/f., harbour centre , 25 harbour road wanchai, hong kong phone: +852-2585-4600 fax: +852-2827-4346 telex: 65542 epsco hx epson (china) co., ltd. shenzhen branch 12/f, dawning mansion, keji south 12th road, hi- tech park, shenzhen phone: +86-755-2699-3828 fax: +86-755-2699-3838 epson taiwan technology & trading ltd. 14f, no. 7, song ren road, ta i p e i 11 0 phone: +886-2-8786-6688 fax: +886-2-8786-6660 epson singapore pte., ltd. 1 harbourfront place, #03-02 harbourfront tower one, singapore 098633 phone: +65-6586-5500 fax: +65-6271-3182 seiko epson corporation korea office 50f, kli 63 bldg., 60 yoido-dong youngdeungpo-ku, seoul, 150-763, korea phone: +82-2-784-6027 fax: +82-2-767-3677 gumi office 2f, grand b/d, 457-4 songjeong-dong, gumi-city, korea phone: +82-54-454-6027 fax: +82-54-454-6093 seiko epson corporation semiconductor operations division ic sales dept. ic international sales group 421-8, hino, hino-shi, tokyo 191-8501, japan phone: +81-42-587-5814 fax: +81-42-587-5117 document code: 411135202 first issue may 2007 revised april 2008, japan c

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